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| HV2321 Low Charge Injection, 8-Channel, Unipolar, Negative High Voltage, Analog Switch With Bleed Resistors Features Low on-resistance, 14 max. Integrated bleed resistors on the outputs 3.3 or 5.0V CMOS input logic level 20MHz data shift clock frequency Very low quiescent power dissipation -10A Low parasitic capacitance DC to 10MHz analog signal frequency -60dB typical off-isolation at 5.0MHz CMOS logic circuitry for low power Excellent noise immunity Cascadable serial data register with latches General Description The Supertex HV2321 is a low charge injection, 8-channel, unipolar, negative high voltage, analog switch integrated circuit (IC) with bleed resistors. The device can be used in applications requiring high voltage switching controlled by low voltage signals, such as NDT metal flaw detection, medical ultrasound imaging, piezoelectric transducer drivers, and printers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. Data is input into an 8-bit shift register and then retained in an 8-bit latch. To reduce any possible clock feed-through noise, the latch enable bar should be left high until all bits are clocked in. Data is clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. Applications NDT metal flaw detection Medical ultrasound imaging Piezoelectric transducer drivers Inkjet printer heads Optical MEMS modules Block Diagram LATCHES D LE CLR LEVEL SHIFTERS OUTPUT SWITCHES SW0 CLK D LE CLR SW1 DIN 8-BIT SHIFT REGISTER D LE CLR SW2 DOUT D LE CLR SW6 D LE CL SW7 VDD GND LE CLR VNN VPP RGND HV2321 Ordering Information 48-Lead LQFP Device HV2321 7x7mm body, 1.6mm height (max),0.50mm pitch Pin Configuration HV2321FG-G -G indicates package is RoHS compliant (`Green') 48 1 48-Lead LQFP (FG) Absolute Maximum Ratings Parameter VDD logic supply VPP-VNN differential supply VPP positive supply VNN negative supply Logic input voltage Analog signal range Peak analog signal current/channel Storage temperature Power dissipation Value -0.5V to +7.0V 260V -0.5V to VNN+260V +0.5V to -250V -0.5V to VDD +0.3V VNN to VPP 4.5A -65C to 150C 1.0W Product Marking Top Marking YYWW HV2321FG LLLLLLLLL Bottom Marking CCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = "Green" Packaging *May be part of top marking 48-Lead LQFP (FG) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Operating Conditions Sym VDD VPP - VNN VPP VNN VIH VIL VSIG TA Parameter Logic power supply voltage Supply voltage differential Positive driver supply Negative high voltage supply High level input voltage Low-level input voltage Analog signal voltage peak-to-peak Operating free air temperature Value 3.0V to 5.5V 240V +15V to +50V -100V to -225V 0.9VDD to VDD 0V to 0.1VDD VNN +10V to VPP -10V 0OC to 70OC Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. VSIG must be VNN VSIG VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. 2 HV2321 DC Electrical Characteristics (Over operating conditions unless otherwise specified ) 0OC Sym Parameter Min RONS Small signal switch on-resistance RONS RONL RINT ISOL VOS(ON) IDDQ IPPQ INNQ IDDQ IPPQ INNQ Small signal switch on-resistance matching Large signal switch on-resistance Output switch bleed resistor Switch off-leakage per switch DC offset switch on Quiescent VDD supply current Quiescent VPP supply current Quiescent VNN supply current Quiescent VDD supply current Quiescent VPP supply current Quiescent VNN supply current ISW Switch output peak current fSW Output switching frequency IPP Average VPP supply current INN Average VNN supply current IDD IDDQ ISOR ISINK CIN Average VDD supply current Quiescent VDD supply current DOUT source current DOUT sink current Logic input capacitance 0.45 0.45 4.5 10 10 Max -20 5.0 300 500 Min 30 0.45 0.45 - +25OC Typ 5.0 9.2 50 1.0 100 100 4.5 4.0 2.0 5.6 5.6 5.6 5.8 5.8 5.8 0.70 0.70 Max 14 14 15 15 23 23 20 70 10 300 500 50 50 -50 50 50 -50 50 7.5 7.5 7.5 7.5 7.5 7.5 4.5 10 10 +70OC Units Conditions Min 0.40 0.40 Max 20 15 300 500 4.5 10 10 mA A mA mA pF mA mA kHz A VSIG duty cycle < 0.1%, 1.0s VPP = +50V VNN = -190V VPP = +40V VNN = -200V VPP = +15V VNN = -225V Duty cycle = 50% VPP = +40V VNN = -200V VPP = +50V VNN = -190V VPP = +15V VNN = -225V VPP = +40V VNN = -200V VPP = +50V VNN = -190V VPP = +15V VNN = -225V 50kHz output switching frequency with no load A All switches on, ISW = 5.0mA A All switches off % K A mV ISIG = 5.0mA ISIG = 200mA ISIG = 5.0mA ISIG = 200mA ISIG = 5.0mA ISIG = 200mA VPP = +50V VNN = -190V VPP = +40V VNN = -200V VPP = +15V VNN = -225V ISIG = 5.0mA, VPP = +40V, VNN = -200V VSIG = 0V, ISIG = -1.0A Switch outputs to RGND pin VSIG = VPP -10V, VNN +10V 100K load VOS(OFF) DC offset switch off 50kHz output switching frequency with no load fCLK = 5.0MHz, VDD = 5.0V All logic inputs are static VOUT = VDD -0.7V VOUT = 0.7V --- 3 HV2321 AC Electrical Characteristics (Over recommended operating conditions: VDD = +5.0V, tR = tF 5.0ns, 50% duty cycle, VPP = +40V, VNN = -200V, CLOAD = 20pF, unless otherwise specified) 0OC Sym tSD tWLE Parameter Min Set up time before LE rises Time width of LE tDO tWCL tSU tH fCLK tR, tF tON tOFF dv/dt Clock delay time to data out Time width of CLR Set up time data to clock Hold time data from clock Clock frequency Clock rise and fall times Turn on time Turn off time Maximum VSIG slew rate -30 KO Off isolation -58 KCR IID Switch crosstalk Output switch isolation diode current Output voltage spike QC Charge injection 300 -58 -60 50 5.0 5.0 20 20 20 -30 2.0 2.0 55 Max Min 25 - +25OC Typ 56 12 78 30 21 7.0 -33 18 70 59 115 71 115 56 115 1950 1890 2110 Max 8.0 20 50 5.0 5.0 20 20 20 300 - +70OC Units Conditions Min 2.0 -30 -58 Max ns ns ns MHz 50 5.0 5.0 20 20 20 dB 300 pC mV dB mA pF pF V/ns ns s ns ns ns --VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V --VDD = 3.0V VDD = 5.0V VDD = 3.0 or 5.0V VDD = 3.0V VDD = 5.0V --VSIG = -100V, RLOAD = 10k to GND VPP = +40V, VNN = -200V VPP = +50V, VNN = -190V VPP = +15V, VNN = -225V f = 5.0MHz, VOFFSET = -15V, 1.0K/15pF load f = 5.0MHz, VOFFSET = -15V, 50 load f = 5.0MHz, VOFFSET = -15V, 50 load 300ns pulse width, 2.0% duty cycle f = 1.0MHz, VOFFSET = -15V f = 1.0MHz, VOFFSET = -15V VPP = +40V, VNN = -200V, RLOAD = 50 VPP = +50V, VNN = -190V, RLOAD = 50 VPP = +15V, VNN = -225V, RLOAD = 50 VPP = +40V, VNN = -200V, VSIG = 0V VPP = +50V, VNN = -190V, VSIG = 0V VPP = +15V, VNN = -225V, VSIG = 0V CSG(OFF) Off capacitance SW to GND CSG(ON) +VSPK -VSPK +VSPK -VSPK +VSPK -VSPK On capacitance SW to GND 4 HV2321 Truth Table D0 L H L H L H L H L H L H L H L H X X X X X X X X X X X X X X X X D1 D2 D3 D4 D5 D6 D7 LE L L L L L L L L L L L L L L L L H X CLR L L L L L L L L L L L L L L L L L H Hold Previous State All Switches Off SW0 Off On Off On Off On Off On Off On Off On Off On Off On SW1 SW2 SW3 SW4 SW5 SW6 SW7 Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch. 4. DOUT is high when data in the shift register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs. Logic Timing Waveforms DN-1 DATA IN 5 0% DN 50% DN+1 LE 50% 50% t WLE t SD CLOCK t SU DATA O UT 50% th t DO 50% t OFF 50% t ON OFF V OUT (TYP ) ON 5 0% t WCL 5 0% 90% 1 0% CLR 5 HV2321 Test Circuits 0V -125V PP PP DD PP PP DD PP PP DD VOFFSET VOFFSET PP PP PP DD PP DD PP PP DD PP PP DD PP PP DD 6 HV2321 Pin Configuration - 48-Lead LQFP (FG) Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name SW5 NC SW4 NC SW4 NC NC SW3 NC SW3 NC SW2 NC SW2 NC SW1 NC SW1 NC SW0 NC SW0 NC VPP Pin # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name VNN NC RGND GND VDD NC NC NC DIN CLK LE CLR DOUT NC SW7 NC SW7 NC SW6 NC SW6 NC SW5 NC 7 HV2321 48-Lead LQFP Package Outline (FG) 7x7mm body, 1.6mm height (max.), 0.50mm pitch D D1 E E1 Note 1 (Index Area D1/4 x E1/4) L2 48 1 b e L L1 Seating Plane Gauge Plane Top View View B A A2 Seating Plane A1 View B Side View Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension (mm) NOM MAX A 1.40* 1.60 A1 0.05 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 D 8.80 9.00 9.20 D1 6.80 7.00 7.20 E 8.80 9.00 9.20 E1 6.80 7.00 7.20 e 0.50 BSC L 0.45 0.60 0.75 L1 1.00 REF L2 0.25 BSC 0O 3.5O 7O JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. Drawings are not to scale. (The package drawing (s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV2321 NR013108 8 |
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